A general purpose processor (CPU) uses a pre-defined instruction-set architecture (ISA) to run common workloads with a reasonable performance. For certain workloads, this performance is CPU-bound, meaning that the pre-defined instructions are not able to use the silicon efficiently. In such cases, an accelerator including GPUs or FPGAs would be appropriate to improve the performance and efficiency.
The goal of this project is to analyse the instruction usage behaviour of representative workloads, provide insights on ISA research, and potentially create an alternative ISA or an extension to x86, RISC-V, SPARC, etc. A fine-tuned instruction extension could accelerate certain workloads, which can be used alongside modular ISAs like RISC-V.
This project will focus mostly on the analytics aspect of the instruction behaviour, and will involve instrumentation tools. The student will write C/C++ code and provide and visualise analytics relating to the distribution of instructions etc. A familiarity with the codebase of the GCC toolchain is a plus. The instruction implementation itself, such as using a hardware-level description language (HDL), is out of the scope of this specific project.